Method for programming redundancy registers in a row redundancy

Details Method for programming redundancy registers in a row redundancy Method for programming redundancy registers in a row redundancy

1995-02-16

1997-08-19

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523003, 36518509, 36518511, 371 102, 371 103, G11C 2900

Patent

active

056595093

ABSTRACT:
A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals. The method provides for: applying to the row address lines the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals for selecting the register which is to be programmed; applying to a further column address line a first logic level to select for programming in the selected memory register, a first subset of memory cells; enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset of memory cells; applying to at least a subset of the row address lines the address of the second defective row of the pair; applying to the further column line a second, opposite logic level to select for programming, in the selected memory register, at least a group of memory cells of the second subset of the two subsets of memory cells; and enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset of memory cells.

REFERENCES:
patent: 4358833 (1982-11-01), Folmsbee et al.
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 5337277 (1994-08-01), Jang

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