Method of fabricating thin-film transistors

Details Method of fabricating thin-film transistors Method of fabricating thin-film transistors

1995-06-06

1997-08-19

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438163, H01L 21336, H01L 29786

Patent

active

056588054

ABSTRACT:
The off-state leakage current, threshold voltage and on-state current of a thin-film transistor (TFT) can be degraded by operation at high drain bias voltages, e.g. above 15 volts. Such degradation is significantly reduced by forming the drain (6) as a highly-doped semiconductor electrode layer (56) on part of an intermediate lower-doped layer (55) on the semiconductor film (2) forming the TFT channel. The drain electrode layer (56) is laterally separated from the transistor channel. An area (A) of the intermediate layer (55) not overlapped by the electrode layer (56) nor modulated by the gate (4) extends from the drain electrode layer (56) towards the gate (4) so as to provide along the intermediate layer (55) a low-doped field-relief region in at least part of the area of lateral separation. The TFTs may be, for example, of the coplanar type or even of the inverted staggered type.

REFERENCES:
patent: 5488005 (1996-01-01), Han et al.
Kamins et al., "Monolithic Integrated Circuit Fabricated in Laser-Annealed Polysilicon", IEEE Transactions on Electron Devices, vol. ED27, No. 1, Jan., 1980, pp. 290-293.

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