Non-volatile semiconductor memory having improved erasure charac

Details Non-volatile semiconductor memory having improved erasure charac Non-volatile semiconductor memory having improved erasure charac

1992-10-20

1994-11-15

Ngo, Ngan Van

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257315, H01L 2968, H01L 2978

Patent

active

053650980

ABSTRACT:
A floating gate is formed via a first gate insulating film over the channel region between source and drain regions which are formed in a semiconductor substrate. A control gate is formed via a second gate insulating film over the floating gate. A low impurity concentration semiconductor region is formed on the side of the control gate which faces the floating gate. When erasing, a depletion layer is produced in this low impurity concentration region and further saturates the erase characteristic for the erasure time by decreasing the capacitance between the control gate and the floating gate.

REFERENCES:
patent: 4947221 (1990-08-01), Stewart et al.
Patent Abstracts of Japan, vol. 11, No. 20 (E-472) (2467) Jan. 20, 1987, and Japanese Patent Application No. 61-190981, Aug. 25, 1986.
Patent Abstracts of Japan, vol. 13, No. 74 (E-717) Feb. 20, 1989, and Japanese Patent Application No. 63-255964, Oct. 24, 1988.

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