Semiconductor memory device multiplying system clock for storing

Details Semiconductor memory device multiplying system clock for storing Semiconductor memory device multiplying system clock for storing

1998-07-07

2000-09-19

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711167, 711171, 711172, G06F 1316

Patent

active

061227056

ABSTRACT:
A variable data-length memory device has memory blocks (27a-27d/26a-26d) storing n-bit data codes, an n-bit data output register (29b) connected between the memory blocks and an n-bit data bus (23a) and a frequency multiplier (29a) responsive to a control signal (CTL1) indicative of (2.sup.m .times.n) bit data code to be supplied to a logic unit (24) for changing a frequency of an internal clock signal (CLKin) 2.sup.m times larger in frequency than a system clock (CLKex); although the memory blocks and the logic unit transfer the n-bit data codes and the (2.sup.m .times.n) bit data code in synchronism with the system clock, the data transfer between the output register and the memory blocks is controlled by the internal clock signal so as to convert the (2.sup.m .times.n) bit data code to the n-bit data code or data codes.

REFERENCES:
patent: 4766538 (1988-08-01), Miyoshi
patent: 5671372 (1997-09-01), Price et al.
patent: 5761478 (1998-06-01), Chen et al.
patent: 5781918 (1998-07-01), Lieberman et al.

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