Semiconductor memory device capable of high speed plural paralle

Details Semiconductor memory device capable of high speed plural paralle Semiconductor memory device capable of high speed plural paralle

1997-09-29

2000-09-19

Nelms, David

Static information storage and retrieval

Systems using particular element

Capacitors

36518909, G11C 1121

Patent

active

061221902

ABSTRACT:
A semiconductor memory device having a memory cell array, in which each of memory cell N-channel transistors formed in a P-type well has a source connected to a storage node of cell capacitor and a drain connected to a bit line. The potential levels of the well and a cell plate of the cell capacitor are controlled independently. The potential control circuit is capable of changing the potential level of the well from a predetermined negative level to a predetermined positive level so that charges can be transmitted to each of the storage node through the well. Write data for testing are collectively written to a plurality of memory cells.

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