Semiconductor memory device with reduced read time and power con

Details Semiconductor memory device with reduced read time and power con Semiconductor memory device with reduced read time and power con

1995-12-07

1997-08-05

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

36518912, 36523003, G11C 1124

Patent

active

056549121

ABSTRACT:
A semiconductor memory device comprises a memory array in which word lines are driven by a single decoder or a plurality of memory arrays driven by a plurality of decoders operating with the same row address, in the memory array or memory arrays memory cell units in which a plurality of memory cells are connected in series being arranged in the form of an array, a plurality of sense amplifier arrays constituted by arranging a plurality of sense amplifiers each provided for a pair of bit lines or a plurality of pairs of bit lines to read out data from the memory cells of the memory cell arrays, the sense amplifier arrays being divided into a plurality of blocks, and the blocks corresponding to one memory cell array, a register array having a plurality of registers for storing data read out by the plurality of sense amplifiers, the register array being divided into a plurality of blocks, and the blocks corresponding to the sense amplifier block and one memory cell array, and a control circuit for independently controlling the blocks of the sense amplifier arrays and the register array and independently reading out data from the registers in the blocks.

REFERENCES:
patent: 5369612 (1994-11-01), Furuyama
patent: 5418750 (1995-05-01), Shiratake et al.
patent: 5467303 (1995-11-01), Hasegawa et al.
patent: 5477071 (1995-12-01), Hamamoto et al.
patent: 5537347 (1996-07-01), Shiratake
1993 Sympsium on VLSI Circuits Digest of Technical Papers, pp. 59-60, May 1993, Y. Takai, et al., "250MBYTE/SEC Synchronous DRAM Using a 3-Stage-Pipelined Architecture".
1991 IEEE International Solid Stats Circuits Conference, pp. 106-107 and 297, Katsutaka Kimura, et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture".

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