Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-12-18
2000-05-09
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711170, 3952002, G06F 1300
Patent
active
060617683
ABSTRACT:
A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. The determined presence of one or more stored data frames is used to arbitrate storage of tracking information by either the read controller or the write controller into a holding register used to determine a read status for the random access memory.
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Kuo Jerry Chun-Jen
Lai Po-Shen
Niu Autumn Jane
Advanced Micro Devices , Inc.
Cabeca John W.
Tzeng Fred F.
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