Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1998-12-02
2000-09-19
Bowers, Charles
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438735, 438719, 438714, 257693, 257687, H01L 2100
Patent
active
061211567
ABSTRACT:
Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1. The actual devices are then formed using the same or substantially the same process parameters as were used in forming the sacrificial topology of the monitor according to the present invention, thus insuring that properly formed contact holes, vias and/or trenches will also be formed in the actual device or devices.
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Boonstra Thomas
Brownell David J.
Crow David A.
Shamble Edward M.
Bowers Charles
Cypress Semiconductor Corporation
Schillinger Laura M
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