Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1983-03-30
1987-11-10
Harkcom, Gary V.
Static information storage and retrieval
Read/write circuit
Data refresh
364900, G11C 1300
Patent
active
047062215
ABSTRACT:
A new method of refreshing a dynamic RAM, uses relatively simple circuitry. Refreshing of the dynamic RAM can be implemented while smoothly accessing any a real-time based high-speed devices such as a floppy disc driver.
In a microprocessor system comprising a central processing unit (CPU), a dynamic RAM, and a plurality of input/output ports, a refreshing process of the dynamic RAM can occur in one of two modes. When input/output (I/O) accesses are not being performed by the CPU, a burst mode refreshing process takes place. However, when input/output (I/O) accesses are to be performed, a refreshing process of the dynamic RAM can be implemented within a period while the CPU accesses the input/output (I/O) port addresses.
REFERENCES:
patent: 4158883 (1979-06-01), Kadono et al.
patent: 4172282 (1979-10-01), Richelmann
patent: 4185323 (1980-01-01), Johnson et al.
patent: 4249247 (1981-02-01), Patel
patent: 4317169 (1982-02-01), Panepinto, Jr. et al.
patent: 4357686 (1982-11-01), Scheuneman
Hashimoto Sadakatsu
Satoh Masaharu
Harkcom Gary V.
Lacasse Randy W.
Sharp Kabushiki Kaisha
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