Process for fabricating integrated circuits with dual gate devic

Details Process for fabricating integrated circuits with dual gate devic Process for fabricating integrated circuits with dual gate devic

1998-06-18

2000-09-19

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438655, 438659, 438664, 438592, 438232, 438217, 438199, H01L 218238, H01L 214763, H01L 2144

Patent

active

061211249

ABSTRACT:
The invention is directed to a process for forming p+ and n+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected hobo a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is selectively performed in the portion of the metal silicide layer overlying a field oxide region that separates the n-type region from the p-type region in the substrate surface. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.

REFERENCES:
patent: 4420872 (1983-12-01), Solo de Zaldivar
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patent: 5516713 (1996-05-01), Hsue et al.
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5605848 (1997-02-01), Ngaoaram
patent: 5851922 (1998-12-01), Bevk et al.
"0.25 0.25 .beta.m W-Polycide Dual Gate and Buried Metal on Diffusion Layer (BMD) Technology" by Tsukamoto, M. et al., 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 23-24 (Jan. 1997).
"Low Threshold Voltage CMOS Devcies wit Smooth Topography for 1 Volt Applications", by Yu, et al., IEEE, pp. 489-492 (Dec. 11-14, 1997).
"Polycide Dual-Gate Structure for Sub-1/4 Micron Low-Voltage CMOS Technology", by Bevk, J. et al., IEEE, pp. 893-896 (Dec. 10-13, 1995).

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