Static information storage and retrieval – Read/write circuit – Testing
Patent
1999-11-10
2000-05-09
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Testing
365203, G11C 2900
Patent
active
060612851
ABSTRACT:
An SDRAM includes a test precharge signal generator which is activated in response to a test mode signal from a test mode detector. The test precharge signal generator generates a test precharge signal before generation of a precharge signal by a command decoder in response to a write signal from the command decoder. Therefore, in the wafer test using a clock signal having low frequency, it becomes possible to execute precharging operation before the input of the normal precharge command after the input of the write command. As a result, it becomes possible to replace a memory cell, which has low power in terms of write recovery time period, by a redundant memory cell in the wafer test, and to improve production yield.
REFERENCES:
patent: 4608669 (1986-08-01), Klara et al.
patent: 5610867 (1997-03-01), DeBrosse et al.
patent: 5619460 (1997-04-01), Kirihata et al.
Le Vu A.
Mitsubishi Denki & Kabushiki Kaisha
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