Dynamic memory word line driver scheme

Details Dynamic memory word line driver scheme Dynamic memory word line driver scheme

1998-07-27

2000-05-09

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36523006, 365226, G11C 1604

Patent

active

060612770

ABSTRACT:
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels V.sub.ss and V.sub.dd, and for providing a select signal at levels V.sub.ss and V.sub.dd, a high voltage supply source V.sub.pp which is higher in voltage than V.sub.dd, a circuit for translating the select signals at levels V.sub.ss and V.sub.dd to levels V.sub.ss and V.sub.pp and for applying it directly to the word lines for application to the enable inputs whereby an above V.sub.dd voltage level word line is achieved without the use of double boot-strap circuits.

REFERENCES:
patent: 4189782 (1980-02-01), Dingwall
patent: 4442481 (1984-04-01), Brahmbhatt
patent: 4583157 (1986-04-01), Kirsch et al.
patent: 4689504 (1987-08-01), Raghunathan et al.
patent: 4692638 (1987-09-01), Stiegler
patent: 4716313 (1987-12-01), Hori et al.
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4814647 (1989-03-01), Tran
patent: 4857763 (1989-08-01), Sakurai et al.
patent: 4878201 (1989-10-01), Nakaizumi
patent: 4888738 (1989-12-01), Wong et al.
patent: 5010259 (1991-04-01), Inoue et al.
patent: 5031149 (1991-07-01), Matsumoto et al.
patent: 5038327 (1991-08-01), Akaogi
patent: 5150325 (1992-09-01), Yanagisawa et al.
patent: 5347488 (1994-09-01), Matsusbita
patent: 5351217 (1994-09-01), Jeon
patent: 5377156 (1994-12-01), Watanabe et al.
patent: 5751643 (1998-05-01), Lines
Kitsukawa, Goro et al., "An Experimental 1-Mbit BiCMOS DRAM," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.
Ishihara et al., "256k CMOS Dynamic RAM With Static Column Mode of Cycle Time of 50 ns," Nikkei Electronics, Feb. 11, 1985, pp. 243-263.
Kitsukawa, Goro et al., "A 1-Mbit BiCMOX DRAM Using Temperature-Compensation Circuit Techniques," IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 597-601.
Kitsukawa, Goro et al., "A 23-ns 1-Mb BiCMOS DRAM," IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1102-1111.
Nakagome, Yoshinobu et al, "An Experimental 1.5-V 64-Mb DRAM," IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 436-472.
Fujii, Syuso et al., "A 45-ns 16-Mbit DRAM with Triple-Well Structure," IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1170-1174.
Gillingham, Peter et al., "High Speed, High Reliability Circuit Design for Megabit DRAM," IEEE Journal of Solid-State Circuits, vol. 26, No. 8, Aug. 1991, pp. 1171-1175.

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