Level shifter circuit certainly operable although a power supply

Details Level shifter circuit certainly operable although a power supply Level shifter circuit certainly operable although a power supply

1998-11-13

2000-05-09

Santamauro, Jon

Electronic digital logic circuitry

Interface

Logic level shifting

326121, 326 83, 326115, H03K 190175

Patent

active

060609044

ABSTRACT:
In a level shifter circuit comprising two P-channel transistors (MP1, MP2), two N-channel transistors (MN1, MN2), two P-channel transistors (MP3, MP4) and two N-channel transistors (MN3, MN4) which are interposed the P-channel transistors (MP1, MP2) and the N-channel transistors (MN1, MN2), four P-channel transistors (MP7, MP8, MP9, MP10) are connected between node (#1, #2) and VCC/GND signal (IN2) in series to fix node potentials of the N-channel transistors (MN3, M4) to VCC/GND. Connected to the nodes (#1, #2), the P-channel transistors (NP9, MP10) have gates connected to GND as countermeasure of a breakdown voltage BVds. Connected to VCC/GND signal (IN2), the P-channel transistors (MP7, MP8) have gates which are directly connected to an input terminal (IN1) and an output terminal of an inverter (INV1), respectively.

REFERENCES:
patent: 5510731 (1996-04-01), Dingwall
patent: 5619150 (1997-04-01), Briner
patent: 5736869 (1998-04-01), Wei
patent: 5872476 (1998-04-01), Mihara et al.

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