Interrupt handling in an asymmetric multiprocessor computer syst

Details Interrupt handling in an asymmetric multiprocessor computer syst Interrupt handling in an asymmetric multiprocessor computer syst

1992-12-23

1993-09-21

Fleming, Michael R.

Boots, shoes, and leggings

364228, 3642422, 364240, 3642401, 3642412, 3642416, 364DIG1, G06F 1324, G06F 1314, G06F 1516

Patent

active

052476855

ABSTRACT:
Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

REFERENCES:
patent: 4271468 (1981-06-01), Christensen
patent: 4417302 (1983-11-01), Chimienti
patent: 4504906 (1985-03-01), Itaya et al.
patent: 4644465 (1987-02-01), Imamura et al.
patent: 4953072 (1990-08-01), Williams

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