Method of manufacturing a known good die array

Details Method of manufacturing a known good die array Method of manufacturing a known good die array

1994-04-07

1996-08-27

Echols, P. W.

Metal working

Method of mechanical manufacture

Electrical device making

29882, 29884, 83942, 324765, 437183, H05K 334, H01R 4304, H01R 4300

Patent

active

055488846

ABSTRACT:
A known good die array is obtained by a general semiconductor assembly technique to enable mass production of known good die by performing AC and burn-in tests upon a plurality of IC chips simultaneously. The IC chip is attached to the die pad of a lead frame by interposing an adhesive and is wire-bonded. The lead frame is electrically separated from the wire-bonded lead, and the resultant lead frame is inserted into a test jig to perform the AC and burn-in tests. Bonding wires are cut by a cutting apparatus with a diamond and/or a diamond-like blade to attach the plurality of known good die as arrays. The low-cost known good die can be produced in large quantities using ordinary IC chips and can be applied to personal computers beyond the current application field of multichip modules used in super computers.

REFERENCES:
patent: 3444619 (1969-05-01), Loherson
patent: 5006792 (1991-04-01), Malhi et al.
Tim Corbett, "A Process Qualification Plan For KGD" ICEMM Proceedings '93 166-188.
Marshall Andrews, "Known Good Die", Microelectronics And Computer Technology Corporation, Oct. 1992.

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