Method for forming multilevel interconnection in a semiconductor

Details Method for forming multilevel interconnection in a semiconductor Method for forming multilevel interconnection in a semiconductor

1991-07-18

1993-06-15

Maples, John S.

Fishing, trapping, and vermin destroying

437189, 437978, 148DIG43, H01L 21441

Patent

active

052197921

ABSTRACT:
Disclosed is a method for manufacturing a semiconductor device. A multilevel interconnection process for forming a via hole on the first layer electrode and then forming the second layer electrode, comprises the steps of forming the first dielectric layer on the whole surface of the semiconductor substrate where the first layer electrode has been formed, filling the re-entrant by forming the insulating material on the first dielectric layer, laminating a second dielectric layer on the first dielectric layer and the insulating material, forming a via hole by carrying out the photolithography process on the second dielectric layer formed on the first layer electrode, forming an insulating layer on the whole surface of the semiconductor substrate where the via hole has been formed, leaving the spacer on the side wall of the via hole by anisotropically etching the insulating layer, depositing the conductive material on the inside of the via hole whose side wall is enclosed by the spacer and on the whole surface of the second dielectric layer, and patterning the conductive material as a desirable conductive layer shape. Thus, the several problems due to overetching and underetching of the conventional SOG layer can be solved and the slope of the via hole is smaller, thereby improving the step coverage of the conductive material filling the via hole.

REFERENCES:
patent: 4977105 (1990-12-01), Okamoto et al.
patent: 5086016 (1992-02-01), Brodsky et al.

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