Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

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365 63, 36523006, G11C 800

Patent

active

061187232

ABSTRACT:
A semiconductor memory device includes: an array of memory cells that is divided into a plurality of sub-arrays; main word lines; sub-word lines; sub-word select lines; and sub-word drivers. A predetermined number of main word lines are associated with a block of sub-arrays arranged on the same row, and extend over all of these sub-arrays. A set of sub-word lines are provided per sub-array and driven by the same number of sub-word drivers corresponding thereto. Each sub-word select line consists of: a parallel portion, which is placed in parallel to the main word lines; and a plurality of vertical portions crossing the main word lines at right angles. Each sub-word driver is selected by specifying, in combination, one of the main word lines and one of the sub-word select lines. In this arrangement, a difference in signal propagation delay between a main word line and an associated parallel portion of a sub-word select line can be minimized, thus remarkably increasing the operating speed of a semiconductor memory device like a DRAM.

REFERENCES:
patent: 5596542 (1997-01-01), Sugibayashi et al.
patent: 5940343 (1999-08-01), Cha et al.
patent: 5986966 (1999-11-01), Nagata
patent: 6026647 (2000-02-01), Ryu et al.

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