Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM w

Details Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM w Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM w

1999-10-27

2000-09-12

Hoang, Huan

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 36523005, 36518904, G11C 1100

Patent

active

061186899

ABSTRACT:
This invention reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With an unique structure by connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.

REFERENCES:
patent: 5808933 (1998-09-01), Ross, Jr. et al.
patent: 5831896 (1998-11-01), Lattimore et al.

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