Method of monitoring system bus traffic by a CPU operating with

Details Method of monitoring system bus traffic by a CPU operating with Method of monitoring system bus traffic by a CPU operating with

1997-04-02

1998-09-15

Sheikh, Ayaz R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39575001, 711135, 711141, 711142, G06F 132

Patent

active

058093141

ABSTRACT:
The present invention provides a method for maintaining cache coherency while minimizing the power consumption. The method includes operating a first processor in a reduced power mode. While the first processor is operating in a reduced power mode, certain portions of the internal logic in the first processor remain clocked so that the first processor continues to monitor transactions on the system bus. The second processor runs a transaction on the system bus to request data. In the event that the first processor determines that the transaction by the second processor is requesting cache data that is stored in the first processor in a modified state, the first processor signals the second processor. After the current bus cycle is completed, the first processor writes back the modified cache line on the system bus and second processor re-runs the transaction on the system bus.

REFERENCES:
patent: 5481731 (1996-01-01), Conary et al.
patent: 5522058 (1996-05-01), Iwasa et al.
patent: 5537656 (1996-07-01), Mozdzan et al.
patent: 5625826 (1997-04-01), Atkinson
patent: 5632038 (1997-05-01), Fuller
patent: 5640573 (1997-06-01), Gephardt et al.

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