Method of fabricating an improved polycrystalline silicon thin f

Details Method of fabricating an improved polycrystalline silicon thin f Method of fabricating an improved polycrystalline silicon thin f

1990-09-04

1991-11-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 21, 437 29, 437 41, 437101, 148DIG150, H01L 21336

Patent

active

050647750

ABSTRACT:
A process of fabricating an improved transistor on a polycrystalline silicon layer, wherein N and P type dopants, in approximate equal concentrations, are introduced into the layer, and the layer heated. The resultant modified polycrystalline silicon layer inhibits the migration of dopants, used to form the active regions of the device, during subsequent heating steps. An improved field effect transistor having a source region, a drain region, and channel region in a polycrystalline silicon layer, the improvement being that the polycrystalline silicon layer has approximately equal concentrations of N and P type dopants embodied therein, which serves to restrain movement of P/N junctions.

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