Dynamic random access memory having stacked capacitor structure

Details Dynamic random access memory having stacked capacitor structure Dynamic random access memory having stacked capacitor structure

1990-05-17

1991-09-03

Jackson, Jr., Jerome

357 45, 357 51, 357 55, H01L 2968, H01L 2710, H01L 2702, H01L 2906

Patent

active

050458990

ABSTRACT:
A DRAM has a memory cell array in which a plurality of word lines (WL) and a plurality of bit lines (B0) are arranged to orthogonally intersect each other. Memory cells (MC) are arranged in a direction intersecting the bit lines. Capacitors (10) of the memory cells are arranged between the adjacent bit lines. On a silicon substrate (20), the bit line is formed substantially at the same height with the word line and positioned lower than the top of the capacitor. An opening region (15) is formed so that electrode layers (11, 13) of the capacitor do not cover the bit line. The arrangement of the capacitors between the adjacent bit lines allows reduction in the inter-bit-line capacitance. In addition, formation of the region above the bit line which is not covered by the electrode layers of the capacitor makes it possible to reduce the stray capacitance between the capacitor and the bit line. As a result, reduction in amount of the read-out signals which might be caused by an increased bit-line capacitance can be prevented.

REFERENCES:
patent: 4754313 (1988-06-01), Takemae et al.
patent: 4894696 (1990-01-01), Takeda et al.
patent: 4953126 (1990-08-01), Ema
patent: 4970564 (1990-11-01), Kimura
IEDM publication by Kamura et al., "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure", Dec. 1988, pp. 596 to 599.
IEEE Journal of Solid-State Circuits publication by Konishi et al., entitled "Analysis of Coupling Noise Between Adjacent Bit Lines in Megabit DRAMs", vol. 24, No. 1, Feb. 1989, pp. 35 through 42.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64MB DRAM," 1989 Symposium on VLSI Technology Digest of Technical Papers, May 22-25, 1989, pp. 69-70.
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", 1988 IEDM, pp. 592-594.
T. Yoshihara et al., "A Twisted Bit Line Technique for Multi-Mb DRAMs", 1988 IEEE International Solid State Circuits Conference, Feb., 1988, pp. 238-239.

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