Semiconductor memory apparatus having reduced amount of bit line

Details Semiconductor memory apparatus having reduced amount of bit line Semiconductor memory apparatus having reduced amount of bit line

1991-03-25

1993-10-05

Pascal, Robert J.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518906, 365184, 365208, 257369, G11C 1134, H01L 2706

Patent

active

052511723

ABSTRACT:
In a DRAM formed of MOS FETs, respectively different values of substrate bias voltage are applied to transistors of different types of circuit in accordance with the circuit functions, to thereby enable the threshold voltage of the transistors of the sense amplifiers to be brought close to zero, thereby reducing the bit line amplification delay, while maintaining sufficiently high values of threshold voltage for other circuits.

REFERENCES:
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4298960 (1981-11-01), Mitake et al.
patent: 4760560 (1988-07-01), Ariizumi et al.
patent: 4967395 (1990-10-01), Watanabe et al.
patent: 5161121 (1992-11-01), Cho

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