Circuitry and method for latching a logic state

Details Circuitry and method for latching a logic state Circuitry and method for latching a logic state

1992-12-09

1993-10-05

Wambach, Margaret R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307242, 307481, 307353, 377 75, 377 79, H03K 1756, H03K 3289

Patent

active

052508528

ABSTRACT:
A method and circuitry are provided for latching a logic state. A first signal (64) indicates a logic state of an input signal (D) in response to a first transition of a clock signal (72). A second signal (68) indicates a logic state of the first signal (64) in response to a second transition of the clock signal (72). An output signal (Q) indicates the logic state of the first signal (64) in response to the second transition and indicates a logic state of the second signal (68) in response to the first transition.

REFERENCES:
patent: 4066919 (1978-01-01), Huntington
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5132993 (1992-07-01), Nishiura et al.

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