Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-03-31
2000-12-26
Peikari, B. James
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
710 53, 710 57, 711109, 711110, 711149, 711139, G06F 1212
Patent
active
061674885
ABSTRACT:
The present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit suspends operation of the stack cache and causes the spill control unit to store the valid data words in the slow memory unit or data cache unit. After the valid data in the stack cache are saved, the overflow/underflow unit equates the cache bottom pointer to the optop pointer. The overflow/underflow unit then resumes normal operation of the stack cache. If an underflow occurs, the overflow/underflow unit suspends operation of the stack cache. In most underflow conditions, data in stack cache 255 are no longer valid and are not saved. Therefore, the overflow/underflow equates the cache bottom pointer to the optop pointer and resumes operation of the stack cache. For underflows caused by context switches, the data in the stack cache must be saved.
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Gunnison Forrest
Peikari B. James
Sun Microsystems Inc.
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