Self-registered capacitor bottom plate-local interconnect scheme

Details Self-registered capacitor bottom plate-local interconnect scheme Self-registered capacitor bottom plate-local interconnect scheme

1996-07-24

1997-10-21

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

056795955

ABSTRACT:
A method and structure for a lower capacitor electrode for a dynamic random access integrated circuit. A polysilicon gate layer is formed over a thin layer of oxide in a first region of a semiconductor substrate. Another oxide layer is then formed overlying the polysilicon gate layer. A polysilicon layer which was doped by S/D implant including the lower capacitor electrode self-aligns and forms overlying a second region of the semiconductor substrate and over the oxide layer on the polysilicon gate layer. A nitride layer forms on the lower capacitor electrode portion overlying the second region. Exposed portions of the polysilicon layer are then oxidized. The S/D was formed by driving dopant from implanted second layer polysilicon. Portions of polysilicon under the nitride layer corresponding to the lower capacitor electrode oxidizes at a slower rate than the exposed portions of the polysilicon. Such sequence of steps forms a self-aligned lower capacitor electrode for a dynamic random access memory integrated circuit.

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