Semiconductor memory device using one common address bus line be

Details Semiconductor memory device using one common address bus line be Semiconductor memory device using one common address bus line be

1999-12-23

2000-12-26

Dinh, Son T.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365194, 36523006, G11C 800

Patent

active

061669881

ABSTRACT:
A semiconductor memory device, includes: an external address buffer for buffering a first address signal to generate a buffered address signal; a delay for delaying the buffered address signal for a predetermined time to generate a delayed address signal; an internal address buffer for buffering the buffered address signal and the delayed address signal to generate a second address signal; a common address bus line; a switching unit responsive to a control signal for selectively coupling one of the buffered address signal, the delayed address signal and the second address signal as a selected address signal to said common address bus line; and a column predecoder for predecoding the selected address signal transferred via said common address bus line.

REFERENCES:
patent: 5818770 (1998-10-01), Kim et al.
patent: 6018485 (2000-01-01), Cha et al.

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