Suresh Marisetty

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Algorithm for non-volatile memory updates

Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Protection at a particular protocol layer
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Bus grant prediction technique for a split transaction bus in a

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Method and apparatus for handling errors in a processing system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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OS and firmware coordinated error handling using transparent...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Rendezvous of processors with OS coordination

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Profile ID: LFUS-PAI-P-800296

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