4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Shahid S. Ansari

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Method for direct attachment of an on-chip bypass capacitor in a

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent

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Method for direct attachment of an on-chip bypass capacitor in a

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Patent

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System level IC testing arrangement and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Profile ID: LFUS-PAI-P-477432

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