4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Luis A. Basto

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Graphical user interface for testability operation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Insertion of scan hardware

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Method and apparatus for testing embedded cores

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2475211

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