Phase and frequency locked clock generator

Details Phase and frequency locked clock generator Phase and frequency locked clock generator

1999-02-10

2000-12-26

Kinkead, Arnold

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 327160, H03L 706

Patent

active

061666068

ABSTRACT:
A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the time durations of the output clock of a voltage-controlled oscillator with the system clock for N cycles. A correction signal is then generated by comparing these two time durations, and the correction signal is fed back to the voltage-controlled oscillator to eliminate the difference in the time durations. In addition, the voltage-controlled oscillator is also synchronized with the synchronizing signal by using the synchronizing signal as a reset.

REFERENCES:
patent: 4305045 (1981-12-01), Metz et al.
patent: 4675617 (1987-06-01), Martin
patent: 5237290 (1993-08-01), Banu et al.
patent: 6018273 (2000-01-01), Tsyrganovich
patent: 6066988 (2000-05-01), Igura
patent: 6072370 (2000-06-01), Nakamura

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