Nonvolatile semiconductor memory device having a data circuit fo

Details Nonvolatile semiconductor memory device having a data circuit fo Nonvolatile semiconductor memory device having a data circuit fo

1998-04-30

2000-04-25

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular biasing

36518503, 36518517, G11C 700

Patent

active

060551887

ABSTRACT:
A memory cell array includes first and second memory cell groups which are simultaneously selected at the time of erasing. A first bit line is connected to the first memory cell group and a second bit line is connected to the second memory cell group. The first and second bit lines are commonly connected to a data circuit having a latch circuit. First data read from the first memory cell group at the time of erase verify read for the first memory cell group is input to the data circuit and second data read from the second memory cell group at the time of erase verify read for the second memory cell group is input to the data circuit. The data circuit latches data indicating that the erasing operation is completed into the latch circuit when both of the first and second data items indicate that the erasing states of the memory cells are sufficient and latches data indicating that the erasing operation is effected again into the latch circuit when at least one of the first and second data items indicates that the erasing state of the memory cell is insufficient.

REFERENCES:
patent: 5521865 (1996-05-01), Ohuchi et al.
patent: 5652719 (1997-07-01), Tanaka et al.
Kang-Deog Suh, et al; A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme; Journal of Solid-State Circuits vol. 30; Nov. 1995; p. 1149-1156.

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