Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1994-01-26
1995-12-19
Pellinen, A. D.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361 91, 361118, 361127, H02H 904
Patent
active
054774136
ABSTRACT:
An ESD protection structure for p-well technology using nMOS FETs that prevents the lock-on condition normally occurring after one FET of a multi finger structure snaps back. The multifinger structure is contained in a main p-well and channels ESDs of a first polarity from the contact pad to a metal conduit. A resistance is provided between the main p-well and the conduit. Further, the circuit channeling ESDs of a polarity opposite to the first polarity is contained in a second p-well that is distinct from the main p-well. An ESD event causes one of the fingers to snap back. Resulting drain current through that finger generates electron hole pairs in the main p-well by impact ionization. Thus generated holes, traveling to the conduit through the resistance, raise the voltage of the main p-well, and therefore shift the i-v characteristic curves of all the FETs to a point where they no longer exhibit a knee. The absence of a knee prevents the remaining fingers from being locked off by the finger that snapped back. Consequently, all FETs are turned on and ESD protection is provided by all FETs in the main p-well.
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Cypress Semiconductor Corp.
Jackson S.
Pellinen A. D.
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