Computer architecture capable of concurrent issuance and executi

Details Computer architecture capable of concurrent issuance and executi Computer architecture capable of concurrent issuance and executi

1996-09-20

1998-05-12

Geckil, Mehmet B.

Boots, shoes, and leggings

395392, 395384, 364DIG1, 3642318, 3642653, 3642656, G06F 938

Patent

active

057520640

ABSTRACT:
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

REFERENCES:
patent: 3881173 (1975-04-01), Larsen et al.
patent: 4295193 (1981-10-01), Pomerene
patent: 4476525 (1984-10-01), Ishii
patent: 4594655 (1986-06-01), Hao et al.
patent: 4626989 (1986-12-01), Torii
patent: 4739470 (1988-04-01), Wada et al.
patent: 4791557 (1988-12-01), Angel et al.
patent: 4794517 (1988-12-01), Jones et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4875160 (1989-10-01), Brown, III
patent: 4879646 (1989-11-01), Iwasaki et al.
patent: 4926323 (1990-05-01), Baror et al.
patent: 4945511 (1990-07-01), Itomitsu et al.
patent: 4991080 (1991-02-01), Emma et al.
patent: 4991090 (1991-02-01), Emma et al.
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5072364 (1991-12-01), Jardine et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5390355 (1995-02-01), Horst
Pleszkun et al, "The Performance Potential of Multiple Functional Unit Processors", Computer Architecture Conference Proceedings, IEEE May 1988 pp. 37-44.
IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986, pp. 605-608, "Data Bypass Methodology for a Performance Pipeline Processor".
Acosta et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions on Computers, vol. C-35, No. 9, Sep. 1986, pp. 815-828.
Weis et al., "Instruction Issue Logic in Pipelined Computers," IEEE Transactions on Computers, Nov. 1984, pp. 1013-1022.
Tjaden et al., "Detection and Parallel Execution of Independent Instructions," IEEE Transactions on Computers, vol. C-19, No. 10, Oct. 1970, pp. 889-895.

Affiliated with

Also associated with

Rating

Computer architecture capable of concurrent issuance and executi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer architecture capable of concurrent issuance and executi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer architecture capable of concurrent issuance and executi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-994917