Double DRAM cell

Details Double DRAM cell Double DRAM cell

1991-01-28

1991-10-15

James, Andrew J.

357 237, 357 51, H01L 2968, H01L 2978, H01L 2992

Patent

active

050578880

ABSTRACT:
A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.

REFERENCES:
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patent: 4669062 (1987-05-01), Nakano
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patent: 4760036 (1988-07-01), Schubert
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patent: 4864464 (1989-09-01), Gonzalez
patent: 4960723 (1990-10-01), Davies
patent: 4960726 (1990-10-01), Lechaton
patent: 4960727 (1990-10-01), Mattox

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