Fuzzy logic controller with optimized storage organization

Details Fuzzy logic controller with optimized storage organization Fuzzy logic controller with optimized storage organization

1994-03-07

1995-06-06

MacDonald, Allen R.

395 51, 395 61, 395900, G06F 760

Patent

active

054229790

ABSTRACT:
In a fuzzy logic controller, numbers (NI) for linguistic values of the input signal (I1) and first and further parts of input relevance functions (ZL, ZH) of the input signal (I1) can be stored per input signal (I1 . . . I4) in an input memory (I1MEM . . . I4MEM). The numbers for the linguistic values can be fed directly and via incrementing devices (INC1 . . . INC4) to a regulating decoder (RDEC) through a number multiplexer (MUX1a . . . MUX4a), the regulating decoder supplying addresses for a downstream output memory (OMEM). An output signal of the output memory (OMEM) can be fed directly and the first and further parts of the input relevance functions can be fed via relevance function multiplexers (MUX1b . . . MUX4b) to a minimum/maximum circuit (MINMAX). The fuzzy logic controller is distinguished in particular by a very low storage space requirement and is therefore suitable in particular for fuzzy logic controllers with on-chip memories.

REFERENCES:
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VLSI Fuzzy Chip and Inference Accelerator Board Systems Watanabe et al. May 26, 1991 IEEE.
"A VLSI Fuzzy Logic Controller With Reconfigurable Cascadable Architecture", H. Watanabe et al, IEEE Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990, pp. 376-382.

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