Clock distributing circuit

Horology: time measuring systems or devices – Time interval – Electrical or electromechanical

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Details

327147, 327149, 327161, 327295, G04F 800, H03K 513, H03K 500

Patent

active

057516650

ABSTRACT:
A clock distributing circuit, that comprises a clock distribution output circuit for inputting an external clock, outputting a first clock that synchronizes with the external clock, and distributing the first clock to each of load circuits, and a distributed clock input circuit disposed on input stages of all or part of the load circuits and adapted for inputting the first clock and outputting a second clock that synchronizes with the input clock, wherein one of the clock distribution output circuit and the distributed clock input circuit includes a phase difference-voltage converting circuit for converting the phase difference between the input clock and the output clock into a voltage, and a voltage control type delay circuit for delaying the input clock corresponding to an output voltage of the phase difference-voltage converting circuit and for outputting the delayed input clock.

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patent: 5278457 (1994-01-01), Fujita et al.
patent: 5298866 (1994-03-01), Kaplinsfy
patent: 5430397 (1995-07-01), Hiroyuki et al.
Sutoh et al., "Circuit Technique for Skew-Free Clock Distribution", Proceedings of the Custom Integrated Circuits Conference, Santa Clara, May 1-4, 1995, No. Conf. 17, Institute of Electrical and Electronics Engineers, May 1, 1995, pp. 163-166.
Suzuki et al., "A 500 MHZ, 32 Bit, 0.4 MUM CMOS RISC Processor", vol. 29, No. 12, Dec. 1994, pp. 1464-1473.
"Nikkei Microdevice", Nikkei PB Company, pp. 81 to 85, Feb., 1993.
"A CMOS 500 . . . ", 1994 Symposium on VLSI, by S. Sidiropoulos.

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