Semiconductor memory device

Static information storage and retrieval – Addressing – Byte or page addressing

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Details

365104, 365204, 36523006, G11C 800

Patent

active

057516570

ABSTRACT:
A semiconductor memory device according to the present invention includes: a memory cell array including a plurality of virtual ground lines, a plurality of bit lines, and a plurality of memory cells arranged in a matrix shape; a selection circuit; a first amplifier circuit; a second amplifier circuit; and a first control circuit and a second control circuit. The first control circuit and the second control circuit selectively charge or discharge those of the plurality of virtual ground lines corresponding to one page in accordance with the input address, the first control circuit and the second control circuit performing the charging or discharging independently of each other.

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