Synchronous type semiconductor memory device having internal ope

Details Synchronous type semiconductor memory device having internal ope Synchronous type semiconductor memory device having internal ope

1997-01-23

1998-05-12

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365222, 365236, G11C 800

Patent

active

057516553

ABSTRACT:
A memory includes a counter by an operation mode designating command for counting a clock signal, and a circuit for generating an internal operation timing control signal according to the count value of the counter. Activation/inactivation of an internal operation control signal is done in synchronization with a clock signal. It is not necessary to take into consideration the margin with respect to an internal operation control signal. High speed operation can be carried out stably. By providing a signal indicating an internal operation state according to the count value of the counter, the load of an external memory controller for monitoring a command issue timing can be reduced. A high speed operating memory is provided that can reduce the load of a memory controller and that can set the internal operation timing accurately.

REFERENCES:
patent: 5339344 (1994-08-01), Kimura et al.
patent: 5349562 (1994-09-01), Tanizaki
patent: 5396259 (1995-03-01), Pang et al.
patent: 5477491 (1995-12-01), Shirai
patent: 5535169 (1996-07-01), Endo et al.
patent: 5581512 (1996-12-01), Kitamura

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