Sixteen megabit static random access memory (SRAM) cell

Details Sixteen megabit static random access memory (SRAM) cell Sixteen megabit static random access memory (SRAM) cell

1993-02-22

1995-06-06

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 69, 257903, H01L 2910, H01L 2711

Patent

active

054224993

ABSTRACT:
A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of polysilicon and oxide substantially co-planar at their upper surfaces. An access transistor and a thin film load transistor are formed within and adjacent to first and second regions of the polysilicon, respectively, and yet a third, pull down transistor is formed within and adjacent to a third polysilicon region. The thin film transistor includes a thin second layer of polysilicon which is electrically isolated from the second one of the polysilicon regions and is doped to form therein source, drain and channel regions. Advantageously, the thin film transistor is formed on this substantially planar surface, thereby improving process yields and device performance. In a preferred embodiment of the invention, a thick oxide layer is formed and retained over the upper surface of the access transistor, and the thin second layer of polysilicon is extended over this thick oxide layer where it is connectable to a source of supply voltage. In this manner, the thick oxide layer operates to capacitively decouple the access transistor from the supply voltage. Also in a preferred embodiment of the invention, the second layer of polysilicon is extended over the substantially co-planar surfaces described above and into contact with the third polysilicon region to establish an electrical connection between the thin film transistor drain and the pull down transistor gate. Also in a preferred embodiment of the invention, the second polysilicon region includes a buried contact to the silicon substrate which establishes a circuit node for the SRAM cell electrically joining a pull down transistor gate, a pull down transistor drain, and thin film transistor gate, and an access transistor drain.

REFERENCES:
patent: 4905064 (1990-02-01), Yabu et al.
patent: 5034797 (1991-07-01), Yamanaka et al.
patent: 5055904 (1991-10-01), Minami et al.
patent: 5194749 (1993-03-01), Meguro et al.
patent: 5210429 (1993-05-01), Adun

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