Process for forming a static-random-access memory cell

Details Process for forming a static-random-access memory cell Process for forming a static-random-access memory cell

1994-04-25

1995-06-06

Thomas, Tom

Fishing, trapping, and vermin destroying

437 56, 437 57, 437 89, 437203, H01L 2170

Patent

active

054222966

ABSTRACT:
An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.

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patent: 5256588 (1993-10-01), Witek et al.
patent: 5285093 (1994-02-01), Lage et al.
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Wolf; Silicon Processing for the VLSI ERA; vol. 2; pp. 72-75 (1990).
Eklund, et al.; "A 0.5 .mu., BiCMOS Technology for Logic and 4 Mbit-class SRAM's," IEDM: pp. 425-428 (1989).

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