Microprocessor with a cache memory in which validity flags for f

Details Microprocessor with a cache memory in which validity flags for f Microprocessor with a cache memory in which validity flags for f

1987-11-13

1990-07-17

Shaw, Gareth D.

Boots, shoes, and leggings

36424341, 3642434, 3649642, G06F 1202, G06F 930, G06F 1300

Patent

active

049425218

ABSTRACT:
When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the consecutive addresses and the result is stored. When the consecutive addresses are to be accessed, the hit is determined relying upon the result that is stored without effecting the cache memory reference. In the case of mishit, the external memory is readily accessed to shorten the overhead time required for the cache memory reference. Therefore, the access time can be shortened in average.

REFERENCES:
patent: 4363095 (1982-12-01), Woods et al.
patent: 4424561 (1984-01-01), Stanley et al.
patent: 4445172 (1984-04-01), Peters et al.
patent: 4586130 (1986-04-01), Butts, Jr. et al.
patent: 4602368 (1986-07-01), Circello et al.
patent: 4670839 (1987-06-01), Pilat et al.
patent: 4724518 (1989-02-01), Steps
patent: 4811209 (1989-03-01), Rubinstein

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