Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

1991-07-15

1992-12-22

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, G11C 700, G11C 1134

Patent

active

051738740

ABSTRACT:
In writing data in a selected memory cell in an EPROM, MOSFETs constituting a write circuit are controlled by a reference voltage and an output from a voltage dividing circuit in accordance with a write data so that the limited voltage and the limited current of the load line used can be set as desired. This prevents an excess current from being supplied to the drain electrode of a memory cell so that the EPROM can be fabricated without deteriorating the reliability of the memory cell. Further, the wirings for connecting a write voltage terminal with the write circuit and the voltage dividing circuit are individually provided so that the width of the wirings, i.e., the wiring area in the EPROM can be reduced. This permits the EPROM to be integrated with high density.

REFERENCES:
patent: 4597062 (1986-06-01), Asano et al.
patent: 4910710 (1990-03-01), Kobatake
patent: 4924438 (1990-05-01), Kobatake
patent: 4937787 (1990-06-01), Kobatake
patent: 4979146 (1990-12-01), Yokayama et al.

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