Connection/disconnection control circuit for data lines between

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36523006, G11C 800

Patent

active

054405220

ABSTRACT:
A memory system comprises a plurality of memory groups, a dynamic data line provided for each of the memory groups, a memory controller, a dynamic data line division circuit, and a data transfer controller. The dynamic data line division circuit performs connection and disconnection between the dynamic data lines of two adjacent memory groups. Monitoring the data input/output control of the memory controller, the data transfer controller switches the dynamic data line division circuit to a connection mode only when data transfer occurs between the two adjacent memory groups.

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