Methods of forming channels and vias in insulating layers

Details Methods of forming channels and vias in insulating layers Methods of forming channels and vias in insulating layers

1992-03-24

1992-12-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437187, 437192, 437194, 437229, 437238, H01L 21283, H01L 21306

Patent

active

051734427

ABSTRACT:
Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

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