Phase detector circuit and PLL circuit equipped therewith

Details Phase detector circuit and PLL circuit equipped therewith Phase detector circuit and PLL circuit equipped therewith

1992-11-24

1995-08-08

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331 27, 331 25, 327 2, 327 3, H03L 706

Patent

active

054402743

ABSTRACT:
A phase detector circuit (10) for generating an analog signal (VR) dependent upon the phase difference between two digital signals (VE, VA) includes two NOR circuits (20, 27) to the inputs (18, 26; 28, 24) of which the two digital signals are supplied on the one hand delayed and negated and on the other directly. The output signals of the NOR circuits (20, 27) control two current sources (S1, S2), one of which in the activated state furnishes a constant charge current (I1) for a storage capacitor (C) whilst the other of which leads a constant discharge current (I2) of equal magnitude away from said storage capacitor (C). The charge voltage at said storage capacitor (C) is an analog signal (VR) which represents a measure of the phase deviation between the digital signals (VE, VA).

REFERENCES:
patent: 3610954 (1971-10-01), Treadway
patent: 3614635 (1971-10-01), La Pine
patent: 4122405 (1978-10-01), Tietz et al.
patent: 4178560 (1979-12-01), Maury
patent: 4322643 (1982-03-01), Preslar
patent: 4380083 (1983-04-01), Andersson et al.
patent: 4970475 (1990-11-01), Gillig
patent: 5072131 (1991-12-01), Nakano

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