Semiconductor buffer circuit having compensation for power sourc

Details Semiconductor buffer circuit having compensation for power sourc Semiconductor buffer circuit having compensation for power sourc

1981-12-16

1984-04-17

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307601, H03K 5135, H03K 19017, H03K 19096

Patent

active

044437145

ABSTRACT:
A semiconductor circuit, used as a buffer circuit, has an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit, including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during a standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit. The input stage circuit generates an output clock signal. The semiconductor circuit further comprises a circuit for applying a high level clock signal, having the same phase as the inverted clock sigal and a level higher than the level of the sum of a power source upper limit voltage and a transistor threshold voltage, to transistor gates, whereby the voltage of a point charged during the standby period corresponds to the voltage of the power source throughout the standby period. Thus, delay in the output clock signal, which is the cause of fluctuation of the voltage of the power supply during the standby period, is reduced and high speed access time in the dynamic memory device is accomplished.

REFERENCES:
patent: 3927334 (1975-12-01), Callahan
patent: 4061933 (1977-12-01), Schroeder et al.
patent: 4317051 (1982-02-01), Young, Jr.
patent: 4339672 (1982-07-01), Sato
patent: 4379974 (1983-04-01), Plachno

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