Synchronization regeneration circuit

Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal

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375366, 370510, H04L 700

Patent

active

058090940

ABSTRACT:
An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing. Therefore, when established synchronization is incorrect, it can immediately be corrected.

REFERENCES:
patent: 4748623 (1988-05-01), Fujimoto
patent: 5014272 (1991-05-01), Yoshida
patent: 5107495 (1992-04-01), Kamoi et al.
patent: 5303270 (1994-04-01), Fujii

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