Method and apparatus for generating a target clock signal having

Details Method and apparatus for generating a target clock signal having Method and apparatus for generating a target clock signal having

1998-09-30

2000-12-05

Hjerpe, Richard A.

Computer graphics processing and selective visual display system

Display driving control circuitry

Display power source

345211, G09G 500

Patent

active

061573760

ABSTRACT:
A clock generator circuit which provides for short comparison cycles even if X and Y do not have a large common denominator when a target clock signal having a frequency of (X/Y) times the frequency of a reference clock signal is to be generated. The comparison cycle is shortened by using approximately X/L and Y/L as divisors, instead of X and Y. As X/L and/or Y/L may not equal integers, multiple divisors may be used in a weighted fashion such that the weighted averages equal X/L or Y/L as the case may be.

REFERENCES:
patent: 5841430 (1998-11-01), Kuriko
patent: 5861879 (1999-01-01), Shimizu et al.
patent: 5940061 (1999-08-01), Sato
patent: 6022538 (2000-01-01), Eglit

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