Phase locked loop for extracting clock pulses through wave diffe

Details Phase locked loop for extracting clock pulses through wave diffe Phase locked loop for extracting clock pulses through wave diffe

1992-06-04

1993-10-26

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

331 17, H03D 324

Patent

active

052572935

ABSTRACT:
A phase locked loop extracts a clock signal through a wave differential method, and comprises a phase detector supplied with a sampled signal indicative of a variable discrete level of an input signal for producing a first output signal indicative of a waveform difference calculated from variable discrete levels of the sampled signal and a second output signal indicative of an integral calculated from waveform differences; a detector operative to produce a detecting signal indicative of continuation of the waveform differences less than a reference value; a calculator operative to calculate a virtual integral from integrals for producing a third output signal indicative of the virtual integral, the virtual integral and integrals previously calculated forming a convergent series; a selector operative to transfer the second output signal in the absence of the detecting signal and the third output signal in the presence of the detecting signal; and a series combination of a loop filter, a voltage controlled oscillator and a frequency divider responsive to the second and third output signals for producing the clock signal, thereby decreasing time period for convergence of phase difference.

REFERENCES:
patent: 4984249 (1991-01-01), Long et al.
patent: 5036294 (1991-07-01), McCaslin
patent: 5058142 (1991-10-01), Otsuka
patent: 5079519 (1992-01-01), Ashby et al.
"A low jitter PLL for 2B+D Echo Canceller", Kokumai, Motohiro et al., Proceedings of 1986 Spring Conference of Communication Department of Electronic Communication Society, pp. 2-18.

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