Semiconductor memory device having serial access mode

Details Semiconductor memory device having serial access mode Semiconductor memory device having serial access mode

Filed on

1992-04-06

Date issued

1993-10-26

Examiner

Clawson, Jr., Joseph E.

Patent Class

Static information storage and retrieval

SubClass

Addressing

SubSubClass

Plural blocks or banks

Other Related Categories

36518905, 36518912, 365221, 3652385, 365240, G11C 804

Type

Patent

Status

active

Patent number

052572358

Description

ABSTRACT:
A memory device includes first to Sth (S is an integer of 2 or more) memory cell arrays, first to Sth sense amplifier/latch circuits connected to bit lines of these memory cell arrays, and a latch control circuit for inputting and latching data read out from the memory cell arrays to the sense amplifier/latch circuits. In a serial access mode, when a memory cell in the Pth (P is an integer of 1 to S-1) is selected, storage data read out from memory cells belonging to a row of the selected cell in the (P+1)th memory cell array are input and latched to the Pth and (P+1)th sense amplifier/latch circuit by the latch control circuit. When the Sth memory cell array is selected by the access start address, storage data read out from memory cells belonging to a row of the selected cell in the Sth memory cell array and storage data read out from memory cells belonging to a next row of the selected cell in the first memory cell array are input and latched to the Sth and first sense amplifier/latch circuits, respectively. Data latched by the Pth or Sth sense amplifier/latch circuit are read out from the access start address in an order of column addresses, and data latched by the (P+1)th or first sense amplifier/latch circuit are sequentially read out in response to column addresses, respectively.

REFERENCES:
patent: 4715017 (1987-12-01), Iwahashi
patent: 4891795 (1990-01-01), Pinkham et al.
patent: 4899310 (1990-02-01), Baba et al.
patent: 5018100 (1991-05-01), Yanagisawa
patent: 5021998 (1991-06-01), Suzuki et al.
patent: 5121354 (1992-06-01), Mandalia
"High-Speed SRAMS", Buster Ashmore, et al., IEEE International Solid-State Circuit Conference, 1989, pp. 40-41.

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